Types of processor Key Terms
- Central Processing Unit (CPU)
- Arithmetic Logic Unit (ALU)
- Control Unit (CU)
- Registers
- Program Counter (PC)
- Memory Address Register (MAR)
- Memory Data Register (MDR)
- Current Instruction Register (CIR)
- Accumulator (ACC)
- Buses
- Data Bus
- Address Bus
- Control Bus
- Fetch-Decode-Execute Cycle (FDE Cycle)
- Clock Speed
- Cache Memory
- Number of Cores
- Pipelining
- Von Neumann Architecture
- Harvard Architecture
- Instruction Set
- Machine Code
- Microarchitecture
- Multithreading
- Parallel Processing
- Branch Prediction
- Instruction Pipeline
- Superscalar Architecture
- Out-of-Order Execution
- Speculative Execution
- Hyper-Threading
- Integrated Circuit (IC)
- Semiconductor
- Transistor
- Logic Gate
- Binary Code
- Bit
- Byte
- Word Size
- Instruction Register
- Instruction Decoder
- Execution Unit
- Load/Store Unit
- Floating Point Unit (FPU)
- Branch Target Buffer (BTB)
- Translation Lookaside Buffer (TLB)
- Interrupt
- Interrupt Handler
- Interrupt Vector
- Direct Memory Access (DMA)
- Bus Arbitration
- Bus Contention
- Bus Width
- Bus Speed
- System Clock
- Clock Cycle
- Clock Rate
- Clock Multiplier
- Heat Sink
- Thermal Throttling
- Power Consumption
- Instruction Cycle
- Microcode
- Opcode
- Operand
- Addressing Mode
- Immediate Addressing
- Direct Addressing
- Indirect Addressing
- Indexed Addressing
- Base Addressing
- Relative Addressing
- Stack Pointer
- Frame Pointer
- Instruction Fetch
- Instruction Decode
- Instruction Execute
- Instruction Writeback
- Pipeline Stall
- Pipeline Hazard
- Data Hazard
- Control Hazard
- Structural Hazard
- Cache Hit
- Cache Miss
- Cache Line
- Cache Coherency
- Write-Through Cache
- Write-Back Cache
- Level 1 Cache (L1)
- Level 2 Cache (L2)
- Level 3 Cache (L3)
- Memory Hierarchy
- Primary Memory
- Secondary Memory
- Tertiary Memory
- Virtual Memory
- Memory Management Unit (MMU)
- Page Table
- Page Fault